/*-------------------------------------------------------------------------
  Register Declarations for ATMEL 89x2051 Processors    
  
   Written By - Bernd Bartmann 
    Bernd.Bartmann@picard.isdn.cs.tu-berlin.de (1999)
    based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
    KEIL C compatible definitions are included
    
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the
   Free Software Foundation; either version 2, or (at your option) any
   later version.
   
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
   
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
   
   In other words, you are welcome to use, share and improve this program.
   You are forbidden to forbid anyone else to use, share and improve
   what you give them.   Help stamp out software-hoarding!  
-------------------------------------------------------------------------*/

/* BYTE addressable registers */
sfr at 0x81 STACK_POINTER       ;
sfr at 0x82 DPL                 ;
sfr at 0x83 DPH                 ;
sfr at 0x87 POWER_CONTROL       ;
sfr at 0x88 TIMER_CONTROL       ;
sfr at 0x89 TIMER_MODE          ;
sfr at 0x8A TIMER_0_LO          ;
sfr at 0x8B TIMER_1_LO          ;
sfr at 0x8C TIMER_0_HI          ;
sfr at 0x8D TIMER_1_HI          ;
sfr at 0x90 PORT_1              ;
sfr at 0x98 SERIAL_CONTROL      ;
sfr at 0x99 SERIAL_BUFFER       ;
sfr at 0xA8 INTERRUPT_ENABLE    ;
sfr at 0xB0 PORT_3              ;
sfr at 0xB8 INTERRUPT_PRIORITY  ;
sfr at 0xD0 PSW                 ;
sfr at 0xE0 ACC                 ;
sfr at 0xE0 A                   ;
sfr at 0xF0 B                   ;


/* BIT addressable registers */
/* TCON */
sbit at 0x88 INT_TYPE_0     ;
sbit at 0x89 EXT_INT_0      ;
sbit at 0x8A INT_TYPE_1     ;
sbit at 0x8B EXT_INT_1      ;
sbit at 0x8C TIMER_0_RUN    ;
sbit at 0x8D TIMER_0_FLAG   ;
sbit at 0x8E TIMER_1_RUN    ;
sbit at 0x8F TIMER_1_FLAG   ;

/* SCON */
sbit at 0x98 RX_INT         ;
sbit at 0x99 TX_INT         ;
sbit at 0x9A RX_BIT_9       ;
sbit at 0x9B TX_BIT_9       ;
sbit at 0x9C RX_ENABLE      ;
sbit at 0x9D SERIAL_MODE_2  ;
sbit at 0x9E SERIAL_MODE_1  ;
sbit at 0x9F SERIAL_MODE_0  ;

/* IE */
sbit at 0xA8 EN_EXT0_INT    ;
sbit at 0xA9 EN_TIMER0_INT  ;
sbit at 0xAA EN_EXT1_INT    ;
sbit at 0xAB EN_TIMER1_INT  ;
sbit at 0xAC EN_SERIAL_INT  ;
sbit at 0xAF ENABLE_INT     ;

sbit at 0xB0 RXD            ;
sbit at 0xB1 TXD            ;
sbit at 0xB2 EXT_INT0_IN    ;
sbit at 0xB3 EXT_INT1_IN    ;
sbit at 0xB4 TIMER_0_IN     ;
sbit at 0xB5 TIMER_1_IN     ;
sbit at 0xB6 COMPARATOR     ;

/* IP */ 
sbit at 0xB8 EXT_INT0_PRI       ;
sbit at 0xB9 TIMER0_PRIORITY    ;
sbit at 0xBA EXT_INT1_PRI       ;
sbit at 0xBB TIMER1_PRIORITY    ;
sbit at 0xBC SER_PRIORITY       ;

/* PSW */
sbit at 0xD0 P          ;
sbit at 0xD1 FL         ;
sbit at 0xD2 OV         ;
sbit at 0xD3 RS0        ;
sbit at 0xD4 RS1        ;
sbit at 0xD5 F0         ;
sbit at 0xD6 AC         ;
sbit at 0xD7 CY         ;


/* BIT definitions for bits that are not directly accessible */
/* PCON bits */
#define IDL             0x01
#define PD              0x02
#define GF0             0x04
#define GF1             0x08
#define SMOD            0x80

#define IDL_            0x01
#define PD_             0x02
#define GF0_            0x04
#define GF1_            0x08
#define SMOD_           0x80

/* TMOD bits */
#define M0_0            0x01
#define M1_0            0x02
#define C_T0            0x04
#define GATE0           0x08
#define M0_1            0x10
#define M1_1            0x20
#define C_T1            0x40
#define GATE1           0x80

#define M0_0_           0x01
#define M1_0_           0x02
#define C_T0_           0x04
#define GATE0_          0x08
#define M0_1_           0x10
#define M1_1_           0x20
#define C_T1_           0x40
#define GATE1_          0x80

#define T0_M0           0x01
#define T0_M1           0x02
#define T0_CT           0x04
#define T0_GATE         0x08
#define T1_M0           0x10
#define T1_M1           0x20
#define T1_CT           0x40
#define T1_GATE         0x80

#define T0_M0_          0x01
#define T0_M1_          0x02
#define T0_CT_          0x04
#define T0_GATE_        0x08
#define T1_M0_          0x10
#define T1_M1_          0x20
#define T1_CT_          0x40
#define T1_GATE_        0x80

#define T0_MASK         0x0F
#define T1_MASK         0xF0

#define T0_MASK_        0x0F
#define T1_MASK_        0xF0

/* Interrupt numbers: address = (number * 8) + 3                */
#define EXTI0           0       /* 0x03 external interrupt 0    */
#define TIMER0          1       /* 0x0b timer 0                 */
#define EXTI1           2       /* 0x13 external interrupt 1    */
#define TIMER1          3       /* 0x1b timer 1                 */
#define SINT            4       /* 0x23 serial port 0           */