- PUCE IS still alive - just
hasn't been a lot of progress lately for a number of reasons and partly due
to the fact that neither of us has had much spare time to work on it. As
far as the NES is concerned, we've been tinkering a lot
with the interleaving of CHR and PRG bus accesses and have, at various stages,
had Tennis running with a 'snowy' picture. Unfortunately, we've come to the
conclusion that, with the current flash device, it's not quite fast enough
to support the NES in it's current configuration.
- But that doesn't mean it can't be done with this design! We haven't
loaded the 7x faster SRAM, and faster flash is available. It might be a matter
of waiting a little while, but we're still confident that it can be done.
- So, rather than getting bogged down further with the NES, I've
decided to move on to the relatively straightforward SNES and Chris is going
to tackle the N64. But first we need to go back and redo the flash programming
algorithms properly, since we'll be loading considerably larger rom images!
Given that it's heading towards Xmas now, and the fact that I have a few
other major things on my plate atm, there probably won't be much progress
worth reporting until perhaps late February next year! The good news is that
once I do get back into it, I'll be able to dedicate more time than ever
before to my hobbies, including PUCE!
- NES Tennis running on PUCE! We've only emulated the
PRG bus at this point, but you can see and hear it running with garbled graphics
(basically the same point we got to on our prototype all those months ago).
Next step now is to emulate the CHR bus and multiplex access to the Flash.
- Got the level-converters and a small (4MB) flash loaded. Struggling
with the crappy NIOS UART to get a flash-writer wirtten in C (<2KB on-chip
RAM) that can keep up with the baud clock - not easy. Cobbled together something
barely functional but finally got a 24K NES Tennis ROM image into flash after
a 1/2hr download!
- Downloaded a free UART core in verilog which had a serious BUG! Nothing's ever easy...
- We've now built two (2) boards, loaded with all but SRAM (which
we don't have) and the RS-232 level-converters (which we have the wrong parts
for). We've tested pretty much all of the FPGA I/O and it's All Systems Go
- Unfortunately, we were mistaken in thinking there was sufficient
internal RAM to implement NES Tennis. This means we'll need to get the Flash
write routines going before we can emulate even the simplest NES cartridge.
- Without an operational serial port, it makes it difficult to
get a NIOS up-and-running, which also makes writing Flash routines a real
chore. We'll probably jury-rig a similar part until we can source the right
device in a small MOQ.
- Checkout the HISTORY
page for the first pics of PUCE running!
- Awesome news! We've populated
the board with the power supply, clock circuit and the majority of the passives.
We also took a gamble and, after a practise run on a throw-away component,
we bit the bullet and decided (against good advice) to attempt loading the
FPGA. After almost stuffing it up, I handed the soldering iron over to Chris
and he managed to clean up my mess and it was time to face the moment of
truth... and much to our joy it was recognised as a valid device on the JTAG
chain!!! There's been a few bad joints identified and fixed since then but
we now have blinking lights and the correct test signals on all the NES bus
- Chris had the idea of getting NES Tennis up and running from
the internal SRAM on the FPGA, before we need to load any flash and worry
about writing flash programming routines. We're still working on it, and
I'll post any news of our success as soon as it happens!
- We also hope to borrow a digital camera and get some pictures up soon!
- They're HERE!!! More later...
- I have just sent the PCB file off to be manufactured!!! There'll
probably be a few days' delay with last-minute instructions back-and-forth
but a finished PCB should be less than 3 weeks away now! Here's an image
of the final PCB
- A number of factors have contributed to the delay; selecting
a manufacturer, trying to find a source of the LDO regulators without a MOQ
of 500, and a simple lack of time due to other committments. Up until now,
we've had nothing tangible to show for our efforts (and we started prototyping
this project in January!) - I would expect that having a shiny new PCB in
a few weeks will only spur us on to forge ahead with this project! Plus,
once we get a few boards assembled, there'll be a parallel development effort!
- Just a quick update to let anyone interested know that things are still
progressing, albeit slowly. Cynics would point out that we are at the stage
that many ambitious projects grind to a halt, but rest-assured we have full
intention of going ahead with manufacture. We have spoken to a couple of
manufacturers - we know what sort of outlay is required (and
I've almost fully recovered from the shock) - now we are just getting our
documentation in order in preparation for sending off. Turn-around is in
the order of 10 days once we have submitted enough information and give the
go-ahead. Stay tuned!
- The addition of an expansion connector by Chris has turned out
to be invaluable already - I've just realised it will be quite easy to hook
up a cartridge socket to this, enabling us to use PUCE as a cart dumper as well!
- Updated PCB
image with latest (final?)
- Schematic review is now complete. There were some last-minutes
fixes (pull-ups etc) and some extra filtering/protection on the power supply,
as well as some additional testpoints and provisions to patch to some of
the debug and unused I/O pins on the FPGA should need arise. We've over-engineered
this board as much as we can afford to!
- Now that the circuit is (hopefully) correct and complete, the
remaining task is to check the PCB layout for any obvious errors and any
potential manufacturing issues. I've given up predicting timeframes but a shiny new PCB is not far off now!
- Just a quick WIP report. Schematic review is almost complete. We've identified a few minor enhancements we'd like to make to the PCB to hopefully make the debug/patching (if required) a little easier.
We'll likely also revisit the clock layout which is a little nastier. Pending
these issues we can look at completing the PCB review.
- Last week we did a final clean-up of the layout, and in the
process added an expansion connector for future enhancements (see following).
In theory we won't be touching the layout again, and pending a final review,
should be the PCB that is going out for manufacture!
- We discussed a few future possibilites for the project further
down the track, both in relation to the console incarnation of PUCE and some
exciting possibilities with arcade hardware in a spin-off project. I won't
go into these just yet, but they're both things that haven't (to our knowledge)
been done successfully before! We added an expansion connector which should
allow us to prototype these future designs on the current board.
- Added a 'Pictorial History' of sorts for the project here
- Layout is now complete! (Great work Chris!) Now we can get stuck into review and choose a manufacturer
- at this stage we could expect to be sending the boards out for manufacture
in the next 1-2 weeks!
- A detailed test plan has been drafted.
- Layout continues with another late-night session last night.
The SNES connector and miscellaneous parts at the top of the board have now
been routed - only the N64 connector remains! (PCB)
- BOM assembled and only a few outstanding parts to source/acquire.
- Added email contact details.
- PCB layout nearing completion. Parts list finalised and parts
for two (2) prototypes being sourced and ordered. Hoping to send PCB for
manufacture within 2 weeks. Four (4) PCBs to be manufactured on this run.
- Creation of the PUCE homepage.